Why Advanced Packaging Is the New Strategic Layer in Semiconductors — and How an Industrial Intelligence Layer Accelerates the Roadmap
By Vasu Kalidindi
Cofounder & CTO, Multiscale Technologies, Inc.
Executive Summary
For most of the past fifty years, packaging was the last mile — the unglamorous step between finished silicon and a working part. That era is over. In the AI build-out, packaging has moved from back-end assembly to the layer where memory bandwidth, logic performance, and total system economics are now decided.
Two of the most credible voices in the industry — Akshay Singh, Vice President of Advanced Packaging Technology Development at Micron, and Naga Chandrasekaran, Executive Vice President and Chief Technology and Operations Officer at Intel Foundry — are converging on the same message from opposite ends of the stack. Both are publicly committing their organizations to multi-generation packaging roadmaps with the engineering rigor and customer-centric urgency that the front-end fab has had for decades.
That commitment creates a problem the industry has not yet solved: the empirical, build-and-test development model that carried packaging through the chiplet era cannot move at the cadence the new roadmaps demand. This paper argues that an industrial intelligence layer — a purpose-built AI platform that connects materials, process, structure, and performance across scales — is the missing piece. It is the lever that lets the packaging roadmap actually move at the pace its leaders have committed to.
1. The Memory Side: Packaging Is the Unlock
From Micron’s vantage point, the bottleneck for AI is no longer raw compute — it is the memory wall. Singh has publicly framed advanced packaging as the key enabler of leading-edge AI solutions, and has argued that breaking through the memory wall demands ambidextrous, cross-boundary innovation across the semiconductor ecosystem.
Micron’s High Bandwidth Memory business is the proof point. Stacking thinner-than-paper DRAM die with thousands of through-silicon vias is now the differentiating capability — not the DRAM cell itself. Singh’s posture treats packaging design, materials, and integration as co-equal with process scaling, and he has tied U.S. competitiveness in HBM directly to the CHIPS Act’s National Advanced Packaging Manufacturing Program (NAPMP) investment in advanced packaging leadership.
The implication is that, for memory, the next decade of competitive differentiation will be won or lost in the package.
2. The Logic Side: A Systems Foundry, Not a Wafer Fab
From Intel Foundry’s vantage point, Chandrasekaran is articulating the mirror image. At Intel Foundry Direct Connect 2025, his keynote placed advanced packaging on equal footing with the Intel 18A and Intel 14A process roadmaps — not as a peripheral capability, but as a first-class product line.
The announcements made the strategy concrete:
- EMIB-T, the next-generation embedded bridge engineered specifically for future high-bandwidth memory integration.
- Foveros-R and Foveros-B, expanding the 3D stacking portfolio with more efficient and flexible options for customers.
- A new Chiplet Alliance and an expanded Amkor engagement, giving customers ecosystem-level optionality on advanced packaging.
The framing is consistent: Intel is no longer selling a process node. It is selling a systems foundry in which packaging is the integration layer customers actually buy.
3. Where the Two Narratives Meet
Strip away the company logos and the messages align almost perfectly.
Packaging is now a roadmap, not a step. Both leaders talk in terms of packaging generations — HBM3E and beyond on Micron’s side; EMIB to EMIB-T and Foveros to Foveros-R/B on Intel’s side — with the same multi-year cadence and customer-engagement discipline once reserved for process technology.
HBM is the bridge between them. Singh leads the memory half; Chandrasekaran’s EMIB-T is explicitly designed to land it on the logic side. Neither company can deliver the AI system on its own — and both narratives effectively assume the other.
Cross-boundary collaboration is the operating model. Singh’s “ambidextrous cross-boundary innovation” and Chandrasekaran’s “systems foundry” plus Chiplet Alliance are the same thesis in different vocabularies: the integration problem cannot be solved inside any one company’s walls.
U.S. manufacturing is the shared backdrop. Micron’s HBM packaging buildout and Intel’s Intel 18A volume ramp at Fab 52 in Arizona are two halves of a domestic advanced-packaging supply chain — both leaders position their roadmaps inside the CHIPS Act frame.
4. The Cadence Problem
If packaging is now a multi-generation roadmap, the rate-limiting step is no longer just tooling or capacity — it is the speed of learning.
Every generation (HBM3E to HBM4, EMIB to EMIB-T, Foveros to Foveros-R/B) compresses what used to be a decade of process maturation into eighteen-to-twenty-four-month windows, across thousands of new material, geometry, and integration permutations. Reliability, warpage, thermo-mechanical stress, hybrid-bond interface quality, and yield each become moving targets at the same time.
The traditional answer — physical design-of-experiments, splits, builds, and reliability runs — does not scale to that cadence. It is expensive, serialized, and almost entirely re-learned for every new package architecture. This is the bottleneck that the industry’s current roadmap commitments are silently betting against.
5. The Multiscale Intelligence Layer
Multiscale AI is the industrial intelligence layer purpose-built for this moment. It is designed for problems exactly like advanced packaging — where insight has to travel across materials, process, structure, and performance, and across organizational boundaries.
Compressing the Experiment Cycle
Packaging teams using Multiscale judiciously combine high-fidelity physics simulations with targeted silicon experiments — leveraging emerging Bayesian active-learning methods to decide, at each step, which split is most worth running on a wafer and which can be answered in simulation. The objective is explicit: minimize total development cost while maximizing the insight gained per cycle. Across warpage, thermo-mechanical stress, interconnect reliability, and yield sensitivity, the platform converges teams to a qualified process window with fewer dead-end splits and more shots on goal per quarter. That is the single biggest lever on roadmap velocity.
Connecting the Multi-Physics, Multi-Scale Problem
HBM stacks, hybrid bonds, redistribution layers, bridge dies, and substrates are inherently multi-physics and multi-scale: atomistic interface behavior drives die-level stress, which drives package-level reliability, which drives system-level thermal performance. Singh’s “cross-boundary innovation” and Chandrasekaran’s “systems foundry” both describe a “multiscale” problem where insight has to cross multiple length and time scales and organizational seams.
Multiscale AI is architected for exactly that. A single intelligence layer links materials, process, structure, and performance into one model of the part — so a change in underfill chemistry is connected, in real time, to its downstream impact on HBM yield and EMIB-T reliability.
Turning Manufacturing Data Into a Learning Asset
Micron’s Taiwan packaging hub and Intel’s Arizona and Oregon footprints generate enormous volumes of inline metrology, AOI, and reliability data that today live in silos. Multiscale’s platform converts that exhaust into a continuously improving model of the process — the closed loop that lets each new generation start from the accumulated learning of the last one, instead of restarting from scratch.
Why This Matters Now
The leaders setting the agenda — Singh on the memory side, Chandrasekaran on the logic side — are publicly committing to packaging cadences that the traditional empirical-DOE model cannot sustain. The ecosystems they are building (NAPMP, the Chiplet Alliance, OSAT partnerships with Amkor) are explicitly designed to bring in outside capability where it accelerates the roadmap.
An intelligence layer that compresses development cycles, connects multi-physics data across scales, and turns manufacturing data into reusable learning is not adjacent to that agenda. It is one of the missing pieces it is asking for.
6. Conclusion
Advanced packaging has moved to the strategic center of the semiconductor industry. The two most credible public voices on the subject — Akshay Singh and Naga Chandrasekaran — have converged on the same thesis from opposite ends of the stack: packaging is now a multi-generation roadmap, the integration problem is multi-physics and cross-organizational, and the cadence required will not be met by the empirical methods that brought us here.
Multiscale Technologies was built for exactly this problem. We are not another point tool in the packaging stack. We are the AI substrate that lets the packaging roadmap actually move at the pace its leaders have committed to — turning every wafer, every split, and every reliability run into compounding learning, across materials, process, and performance.
The integration era will reward the companies that learn fastest. We intend to make that the default.
About the Author
Vasu Kalidindi is the Cofounder and Chief Technology Officer of Multiscale Technologies, Inc., the company behind Multiscale AI — a purpose-built industrial intelligence platform for materials, process, and manufacturing teams in the semiconductor and broader industrial sectors.
About Multiscale Technologies
Multiscale Technologies builds vertical AI software for industrial and manufacturing use cases. The Multiscale AI platform centers on two capabilities working in concert: living digital twins of materials, processes, and parts that connect physics, manufacturing data, and performance into one continuously learning model; and AI agents that operate on those twins — running virtual experiments, surfacing root causes, proposing process windows, and accelerating decisions that previously required weeks of physical builds. Together they compress development cycles, raise yield, and turn every wafer and run into compounding learning across product generations. Learn more at multiscale.ai.